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AD7328
TIMING SPECIFICATIONS
V
DD
= 12 V to 16.5 V, V
SS
= 12 V to 16.5 V, V
CC
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, V
REF
= 2.5 V to 3.0 V internal/external,
T
A
= T
MAX
to T
MIN
. Timing specifications apply with a 32 pF load, unless otherwise noted.
1
Table 3.
Limit at T
MIN
, T
MAX
Parameter
V
CC
< 4.75 V
V
CC
= 4.75 V to 5.25 V
Unit
f
SCLK
50
50
kHz min
14
20
MHz max
t
CONVERT
16 × t
SCLK
16 × t
SCLK
ns max
t
QUIET
75
60
ns min
t
1
12
5
ns min
t
22
25
20
ns min
45
35
ns min
t
3
26
14
ns max
t
4
57
43
ns max
t
5
0.4 × t
SCLK
0.4 × t
SCLK
ns min
t
6
0.4 × t
SCLK
0.4 × t
SCLK
ns min
t
7
13
8
ns min
t
8
40
22
ns max
10
9
ns min
t
9
4
4
ns min
t
10
2
2
ns min
t
POWER-UP
750
750
ns max
500
500
μs max
25
25
μs typ
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
2
When using the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t at 20 ns, the mark space ratio needs to be limited to 50:50.
Rev. A | Page 6 of 36
Description
V
DRIVE
≤ V
CC
t
SCLK
= 1/f
SCLK
Minimum time between end of serial read and next falling edge of CS
Minimum CS pulse width
CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
Unipolar input range (0 V to 10 V)
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
SCLK falling edge to DOUT high impedance
DIN set-up time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power up from autostandby
Power up from full shutdown/autoshutdown mode, internal reference
Power up from full shutdown/autoshutdown mode, external reference
) and timed from a voltage level of 1.6 V.
DRIVE
ADD1
1
2
3
4
5
13
14
t
5
15
16
WRITE
REG
SEL1
REG
SEL2
LSB
DON’T
CARE
MSB
ADD0
SIGN
DB11
DB10
DB2
DB1
DB0
t
2
t
6
t
4
t
9
t
10
t
3
t
7
t
8
t
1
t
QUIET
t
CONVERT
SCLK
CS
DOUT
THREE-
STATE
THREE-STATE
DIN
ADD2
3 IDENTIFICATION BITS
0
Figure 2. Serial Interface Timing Diagram
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